Advanced IC Packaging
Advanced packaging is a general group of a variety of distinct techniques like 2.5D , 3D IC, fan-out wafer-level packaging and system-in-packages.
The driver for advanced packaging is correlated with one law called Moore’s Law. Wires are shrinking along with transistors and also the amount of distance that a signal needs to travel from one end of a chip over skinny wires is increasing at each node. By connecting these chips together using fatter pipes, which can be in the form of through-silicon vias, bridges ,interposers or simple wires, the speed of those signals can be increased and the amount of energy required to drive those signals are often reduced.
Technology like Copper hybrid bonding that could pave the way toward next-generation 2.5D and 3D packages.
Many companies working on copper hybrid bonding for packaging like GlobalFoundries, Intel, UMC, TSMC and Samsung are all .
Many packaging options
There are a number of IC package types available in the market. We can use interconnect type, which includes wirebond, flip-chip, wafer-level packaging (WLP) and through-silicon-vias(TSVs). Interconnects are used for connecting one die to another one in packages.
In flip-chip, a sea of larger solder bumps are formed on top of a chip using various process steps. The device is then flipped and mounted on a separate board or die. The bumps land on copper pads form an electrical connection. The dies are bonded using a wafer bonder system.
For most advanced packages, vendors use existing interconnect schemes and wafer bonders. In these packages, the dies are stacked and connected using pillars and copper microbumps . Based on bumps, pillars and solder materials provide small, fast electrical connections between different devices.
The most advanced microbumps and pillars are tiny structures with 40μm to 36μm pitches. A pitch refers to a given space. A 40μm pitch involves a 25μm copper pillar in size having 15μm spacing.
For fine-pitch requirements, the industry uses TCB (thermal compression bonding). A thermal compression bonding (TCB) bonder picks up a die and aligns the bumps to those from another die. It bonds the bumps using heat and force . But, TCB is a slow process.
“A dummy metal spacer microbump is introduced to 3D die-to-wafer stacking to mitigate tilt error of the TCB tool and also for controllingTthe solder deformation, so that electrical resistance and joint formation quality of bonding is same for the different locations of the bonded dies.”
hybrid bonding:-
Hybrid bonding is gaining steam, though. TSMC which is the most vocal proponent, is working on a technology called System on Integrated Chip (SoIC). Using hybrid bonding, TSMC’s SoIC technology enables sub-10μm bonding pitches.
Hybrid bonding for packaging:-
For advanced chip packaging, the industry is also working ondie-to-die copper and die-to-wafer hybrid bonding. This involves stacking a die on a wafer, a die on an interposer, or a die on a die.This is more difficult than wafer-to-wafer bonding.
For die-to-wafer hybrid bonding, the infrastructure to handle dies without particle adders, as well as the ability to bond dies, becomes a major challenge. This is more difficult than wafer-to-wafer bonding.
Indeed, known good die (KGD) is critical. A known good die is an unpackaged part or a bare die that meets a given specification. Without known good die, the package may suffer from low yields or will fail. KGD is important for packaging houses.
Nonetheless, the die-to-wafer hybrid bonding flow is similar to the wafer-to-wafer process. The big difference is the chips are diced and stacked on interposers or other dies using high-speed flip-chip bonders.
1.The entire process starts in the fab, where the chips are processed on a wafer using various equipment. That part of the fab is called the front-end-of-the-line (FEOL).
2.Then, the wafers are shipped for separating the part of the fab called the backend-of-the-line (BEOL). Using different equipment, the wafers undergo a single damascene process in the BEOL.
3.The single damascene process is a mature technology. Basically, that oxide material is deposited on the wafer. Tiny vias are patterned and then etched in the oxide material. The vias are filled with copper using a deposition process.
4.This, in turn, forms copper interconnects or pads on the surface of the wafers. The copper pads are relatively large, measuring on the micrometer(um) scale. This process is somewhat similar to today’s advanced chip production in fabs.
5.That’s only the beginning of the process. Here’s where Xperi’s new die-to-wafer copper hybrid bonding process starts. Others use similar or slightly different flows.
The Next Advanced Packages
Packaging houses are readying their next generation advanced IC packages, paving the way toward new as well as innovative system-level chip designs.
These packages include new versions of 2.5Dand 3D technologies, chiplets,fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers with panels. One is combining fan-out with silicon bridges.
Sneak peak of what’s next in advanced packaging. They include:
TSMC disclosed more details about 3D integration technology of advanced packaging. One version interlaces memory and logic in a tiered 3D architecture for in-memory computing applications.
Using silicon bridges SPIL, and part of ASE, described a fan-out technology . For integrating dies in a package fan-out is used to, and bridges provide the connections from one die to another.
By using new bonding techniques , GlobalFoundries presented a paper on 3D packaging . Other foundries are working on it, as well.
MIT and TSMC presented papers on wafer-scale packaging.
Moving from 2.5D to 3D
At the high-end, the industry traditionally uses 2.5D. In 2.5D, dies are stacked on top of an interposer, which incorporates TSVs. The interposer acts as the bridge between the a board and chips , which provides more I/Os and bandwidth.
TSMC, is working on a technology called System on Integrated Chip (SoIC).
GlobalFoundries is working on hybrid wafer bonding, enabling fine-pitch 3D architectures.
Conclusion:-
In this blog, we covered all you need to know about the Advanced IC Packaging and Race in Advanced IC Packaging with what next?. There a need for better and advanced IC packaging, hybrid bonding and hybrid bonding in packages. We also covered about next advanced IC packages. .We also explained about 2.5D to 3D moving of IC packages.
References-
Author: Shraddha Kshirsagar
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